General-purpose timer (TIMx)
Figure 123. Control circuit in external clock mode 2
f MASTER
CNT_EN
ETR
ETRP
ETRF
Counter clock = CK_CNT = CK_PSC
RM0008
14.3.4
Counter register
Capture/compare channels
34
35
36
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Figure 124. Capture/compare channel (example: channel 1 input stage)
TI1F_ED
to the slave mode controller
TI1
f DTS
filter
downcounter
TI1F
Edge
Detector
TI1F_Rising
TI1F_Falling
0
1
TI1FP1
TI2FP1
01
10
IC1
divider
/1, /2, /4, /8
IC1PS
(from slave mode
ICF[3:0]
TIMx_CCMR1
CC1P
TIMx_CCER
TI2F_rising
(from channel 2)
TI2F_falling
(from channel 2)
0
1
TRC
controller)
11
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
CC1E
TIMx_CCER
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
334/995
Doc ID 13902 Rev 9
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